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Macros</h2></td></tr>
<tr class="memitem:gab5e38a3a5815c463c52461a8f7f52b75"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="separator:gab5e38a3a5815c463c52461a8f7f52b75"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3312e39c24adeb6a06a7408a68a1e80"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaf3312e39c24adeb6a06a7408a68a1e80">XAxiPcie_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;Xil_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for this device.</p>
<p>Some of the registers are configurable at hardware build time such that may or may not exist in the hardware. </p>
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<tr><td colspan="2"><div class="groupHeader">VSECC Register bitmaps and masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">VSECH Register bitmaps and masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bridge Info Register bitmaps and masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bridge Status &amp; Control Register bitmaps and masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Decode Register bitmaps and masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Mask Register bitmaps and masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bus Location Register bitmaps and masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">PHY Status &amp; Control Register bitmaps and masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Root Port Status/Control Register bitmaps and masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Root Port MSI Base Register bitmaps and masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Root Port Error FIFO Read Register bitmaps and masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Root Port Interrupt FIFO Read 1 Register bitmaps and masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Root Port Interrupt FIFO Read 2 Register bitmaps and masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">ECAM Address Register bitmaps and masks</div></td></tr>
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